CPU identification utility v0.04 (engineering release) (C)2016 IC Book Labs.

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CPUID dump
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 Function   Sub-Fnc.   Pass       EAX        EBX        ECX        EDX       

 00000000   00000000   00000000   00000016   756E6547   6C65746E   49656E69  
 00000001   00000000   00000000   000506E1   04100800   7FFAFBFF   BFEBFBFF  
 00000002   00000000   00000000   76036301   00F0B5FF   00000000   00C30000  
 00000003   00000000   00000000   00000000   00000000   00000000   00000000  
 00000004   00000000   00000000   1C004121   01C0003F   0000003F   00000000  
 00000004   00000001   00000000   1C004122   01C0003F   0000003F   00000000  
 00000004   00000002   00000000   1C004143   00C0003F   000003FF   00000000  
 00000004   00000003   00000000   1C03C163   03C0003F   00001FFF   00000006  
 00000005   00000000   00000000   00000040   00000040   00000003   00142120  
 00000006   00000000   00000000   000007F7   00000002   00000001   00000000  
 00000007   00000000   00000000   00000000   029C6FBF   00000000   00000000  
 00000008   00000000   00000000   00000000   00000000   00000000   00000000  
 00000009   00000000   00000000   00000000   00000000   00000000   00000000  
 0000000A   00000000   00000000   07300404   00000000   00000000   00000603  
 0000000B   00000000   00000000   00000001   00000002   00000100   00000004  
 0000000B   00000001   00000000   00000004   00000008   00000201   00000004  
 0000000C   00000000   00000000   00000000   00000000   00000000   00000000  
 0000000D   00000000   00000000   0000001F   00000340   00000440   00000000  
 0000000D   00000001   00000000   0000000F   00000340   00000100   00000000  
 0000000D   00000002   00000000   00000100   00000240   00000000   00000000  
 0000000D   00000003   00000000   00000040   000003C0   00000000   00000000  
 0000000D   00000004   00000000   00000040   00000400   00000000   00000000  
 0000000E   00000000   00000000   00000000   00000000   00000000   00000000  
 0000000F   00000000   00000000   00000000   00000000   00000000   00000000  
 0000000F   00000001   00000000   00000000   00000000   00000000   00000000  
 00000010   00000000   00000000   00000000   00000000   00000000   00000000  
 00000010   00000001   00000000   00000000   00000000   00000000   00000000  
 00000011   00000000   00000000   00000000   00000000   00000000   00000000  
 00000012   00000000   00000000   00000000   00000000   00000000   00000000  
 00000013   00000000   00000000   00000000   00000000   00000000   00000000  
 00000014   00000000   00000000   00000001   0000000F   00000007   00000000  
 00000014   00000001   00000000   02490002   003F3FFF   00000000   00000000  
 00000015   00000000   00000000   00000002   000000B8   00000000   00000000  
 00000016   00000000   00000000   00000898   00000960   00000064   00000000  
 80000000   00000000   00000000   80000008   00000000   00000000   00000000  
 80000001   00000000   00000000   00000000   00000000   00000121   2C100800  
 80000002   00000000   00000000   756E6547   20656E69   65746E49   2952286C  
 80000003   00000000   00000000   55504320   30303020   20402030   30322E32  
 80000004   00000000   00000000   007A4847   00000000   00000000   00000000  
 80000005   00000000   00000000   00000000   00000000   00000000   00000000  
 80000006   00000000   00000000   00000000   00000000   01006040   00000000  
 80000007   00000000   00000000   00000000   00000000   00000000   00000100  
 80000008   00000000   00000000   00003027   00000000   00000000   00000000  
                                                                             
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Maximum standard function number and vendor string , CPUID function # 00000000h
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 Field                          Value, hex    

 Maximum standard CPUID level   00000016      
 CPU vendor string              GenuineIntel  
                                              
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Type,family,model,stepping and standard features , CPUID function # 00000001h
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 Field                                                           Value, hex  

 Type                                                            00          
 Family                                                          06          
 Model                                                           0E          
 Stepping                                                        01          
 Extended family                                                 00          
 Extended model                                                  05          
 Initial local APIC ID                                           04          
 Allocated IDs per package                                       10          
 CLFLUSH line size (bytes)                                       40          
 Brand index                                                     00          
                                                                             
 FPU , x87 floating point unit on chip                           1           
 VME , Virtual mode extension                                    1           
 DE , Debugging extension                                        1           
 PSE , Page size extension                                       1           
 TSC , Time stamp counter                                        1           
 MSR , Model-specific registers                                  1           
 PAE , Physical address extension                                1           
 MCE , Machine check extension                                   1           
 CX8 , CMPXCHG8B instruction                                     1           
 APIC , On-chip local APIC                                       1           
 x , Reserved                                                    0           
 SEP , SYSENTER/SYSEXIT, fast system call instructions           1           
 MTRR , Memory type range registers                              1           
 PGE , Page global enable                                        1           
 MCA , Machine check architecture                                1           
 CMOV , Conditional move instruction                             1           
 PAT , Page attribute table                                      1           
 PSE36 , 36-bit address page size extension (2/4MB pages)        1           
 PSN , Processor serial number (present and enabled)             0           
 CLFSH , CLFLUSH instruction                                     1           
 x , Reserved                                                    0           
 DS , Debug store                                                1           
 ACPI , Thermal monitor and software controlled clock            1           
 MMX , Multimedia extension                                      1           
 FXSR , FXSAVE/FXRSTOR instructions                              1           
 SSE , Streaming SIMD extension                                  1           
 SSE2 , Streaming SIMD extension 2                               1           
 SS , Self-snoop                                                 1           
 HTT , Hyper-Threading technology                                1           
 TM , Thermal monitor                                            1           
 IA64 , Intel Architecture 64 (Itanium)                          0           
 PBE , Pending break enable                                      1           
 SSE3 , Streaming SIMD extension 3                               1           
 PCLM , PCLMULQDQ instruction                                    1           
 DS64 , Debug store for 64-bit branches history                  1           
 MON , MONITOR/MWAIT instructions                                1           
 DSCPL , CPL qualified debug store                               1           
 VMX , Virtual machine extension                                 1           
 SMX , Safer mode extension                                      1           
 EIST , Enhanced Intel SpeedStep technology                      1           
 TM2 , Thermal monitor 2                                         1           
 SSSE3 , Supplemental streaming SIMD extension 3                 1           
 CXTID , L1 context ID                                           0           
 SDBG , Debug Interface MSR for silicon debug                    1           
 FMA , Fused Multiply and Addition instructions                  1           
 CX16 , CMPXCHG16B instruction                                   1           
 xTPR , xTPR update control                                      1           
 PDCM , Performance monitoring and debug capability              1           
 x , Reserved                                                    0           
 PCID , Processor Context identifiers                            1           
 DCA , Direct cache access                                       0           
 SSE41 , Streaming SIMD extension 4.1                            1           
 SSE42 , Streaming SIMD extension 4.2                            1           
 x2AP , x2APIC (extended xAPIC) support                          1           
 MOVBE , MOVBE instruction                                       1           
 PCNT , POPCNT instruction                                       1           
 TSCDL , TSC deadline interrupt                                  1           
 AESNI , Advanced Encryption Standard new instructions           1           
 XSAVE , XSAVE/XRSTOR states, XSETBV/XGETBV instructions         1           
 OSXSV , OS has enabled XSETBV/XGETBV instructions               1           
 AVX , Advanced Vector Extension                                 1           
 F16C , 16-bit Floating Point conversion instructions            1           
 RAND , RDRAND instruction, random number generator              1           
 HPGS , (AMD) Reserved for Hypervisor to indicate Guest status   0           
                                                                             
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Cache and TLB descriptors , CPUID function # 00000002h
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 Found descriptor                                                                                                 Value, hex  

 data TLB, 1G pages, 4-way, 4 entries                                                                             63          
 data TLB, 4K pages, 4 ways, 64 entries                                                                           03          
 code TLB, 2M/4M pages, fully, 8 entries                                                                          76          
 query standard level 0000_0004h instead                                                                          FF          
 code TLB, 4K pages, 8 ways, 64 entries                                                                           B5          
 64 byte prefetching                                                                                              F0          
 L2 code and data TLB, 4K/2M pages, 6 ways, 1536 entries and L2 code and data TLB, 1G pages, 4 ways, 16 entries   C3          
                                                                                                                              
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Processor serial number (PSN) , CPUID function # 00000003h
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 Field   Value, hex  

                     
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Deterministic cache parameters , CPUID function # 00000004h
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 Field                                L1 code   L1 data   L2 unified   L3 unified  

 Cache size (KB)                      32        32        256          8192        
 System coherency line size (bytes)   64        64        64           64          
 Physical line partitions             1         1         1            1           
 Ways of associativity                8         8         4            16          
 Number of sets                       64        64        1024         8192        
 Max. logical CPUs per this cache     2         2         2            16          
 Max. cores per physical package      8         8         8            8           
 Self initializing cache level        1         1         1            1           
 Fully associative cache              0         0         0            0           
 WBINVD/INVD lower caches levels      0         0         0            0           
 Inclusive of lower cache levels      0         0         0            1           
 Direct mapped (0) or complex(1)      0         0         0            1           
                                                                                   
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Enhanced halt states and MONITOR/MWAIT instructions , CPUID function # 00000005h
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 Field                                                Value  

 Smallest monitor line size (bytes)                   64     
 Largest monitor line size (bytes)                    64     
 Enumeration of MONITOR-MWAIT extensions flag         1      
 Interrupt break event for MWAIT (even if disabled)   1      
 Number of C0 sub C-states supported using MWAIT      0      
 Number of C1 sub C-states supported using MWAIT      2      
 Number of C2 sub C-states supported using MWAIT      1      
 Number of C3 sub C-states supported using MWAIT      2      
 Number of C4 sub C-states supported using MWAIT      4      
 Number of C5 sub C-states supported using MWAIT      1      
 Number of C6 sub C-states supported using MWAIT      0      
 Number of C7 sub C-states supported using MWAIT      0      
                                                             
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Thermal, power management and overclocking , CPUID function # 00000006h
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 Feature                                                        Support  

 DTS , Digital temperature sensor                               1        
 TB , Intel Turbo Boost technology                              1        
 ARAT , APIC timer always running                               1        
 R , Reserved                                                   0        
 PLN , Power limit notification controls                        1        
 ECMD , Clock modulation duty cycle extension                   1        
 PTM , Package thermal management                               1        
 HWP-B , Hardware ctrl. perf. states base registers             1        
 HWP-N , HWP notification                                       1        
 HWP-W , HWP activity window                                    1        
 HWP-E , HWP energy performance preference                      1        
 HWP-P , HWP package level request                              0        
 R , Reserved                                                   0        
 HDC , Hardware duty cycling base register                      0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 HCFC , Hardware coordination feedback capability               1        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 PEBP , Processor supports performance-energy bias preference   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
 R , Reserved                                                   0        
                                                                         
 Number of interrupt thresholds in digital thermal sensor       2        
                                                                         
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Additional features , CPUID function # 00000007h
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 Field                                                            Value  

 FSGSBASE , FS,GS base addressing modes                           1      
 TSCADJ , IA32_TSC_ADJUST MSR                                     1      
 SGX , Software guard extensions                                  1      
 BMI1 , Bit manipulation instruction set #1                       1      
 HLE , Hardware lock ellision                                     1      
 AVX2 , Advanced vector extension #2                              1      
 R , Reserved                                                     0      
 SMEP , Supervisor mode execution prevention                      1      
 BMI2 , Bit manipulation instruction set #2                       1      
 EMOVSSTOS , Enhanced REP MOVSB/STOSB                             1      
 INVPCID , Invalidate process context INVPCID instruction         1      
 RTM , Restricted transactional memory                            1      
 PQM , Platform quality of service monitoring                     0      
 DFPUCSDS , Deprecates FPU CS and FPU DS if 1                     1      
 MPX , Memory protection extensions                               1      
 PQE , Platform quality of service enforcement                    0      
 AVX512F , AVX512 foundation                                      0      
 AVX512DQ , AVX512 doublewords and quadwords operations           0      
 RDSEED , Instruction RDSEED, alternative access to RND           1      
 ADX , Instruction set ADX                                        1      
 SMAP , Supervisor mode access prevention                         1      
 AVX512IFMA , AVX512 integer fused multiply and add               0      
 PCOMMIT , Instruction PCOMMIT for cache-NVRAM coherency          0      
 CLFLUSHOPT , Instruction CLFLUSHOPT, optimized cache flush       1      
 CLWB , Instruction CLWB, cache line writevack without flush      0      
 IPT , Intel processor trace                                      1      
 AVX512PF , AVX512 prefetch                                       0      
 AVX512ER , AVX512 exponential and reciprocal                     0      
 AVX512CD , AVX512 conflict detection                             0      
 SHA , Secure hash algorithm                                      0      
 AVX512BW , AVX512 bytes and words operations                     0      
 AVX512VL , AVX512 vector length control                          0      
 PWT1 , Instruction PREFETCHWT1                                   0      
 AVX512VBMI , AVX512 vector byte manipulation                     0      
 R , Reserved                                                     0      
 PKU , Protection keys for user-mode pages                        0      
 OSPKE , OS has set CR4.PKE to enable prot. keys, RDPKRU/WRPKRU   0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
 R , Reserved                                                     0      
                                                                         
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Direct cache access (DCA) , CPUID function # 00000009h
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 Field                                     Value, hex  

 IA32 PLATFORM DCA CAP MSR, bits [31-00]   00000000    
                                                       
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Architectural performance monitoring , CPUID function # 0000000Ah
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 Field                                                           Value  

 Version ID of architectural performance monitoring              4      
 Number of gen. purp. perf. monitoring counter per logical CPU   4      
 Bit width of gen. purp. performance monitoring counter          48     
 Length of bit vector to enumerate architectural PM events       7      
 Core cycle event not available flag                             0      
 Instruction retired event not available flag                    0      
 Reference cycles event not available flag                       0      
 Last level cache reference event not available flag             0      
 Last level cache misses event not available flag                0      
 Branch instruction retired event not available flag             0      
 Branch mispredict retired event not available flag              0      
 Number of fixed-function performance counters                   3      
 Bit width of fixed-function performance counters                48     
                                                                        
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Extended MP topology enumeration , CPUID function # 0000000Bh
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 Field                                                SMT         Core       

 Number of logical processor at this level type       2           8          
 Bits shift right on x2APIC ID to get next level ID   1           4          
 Level number                                         0           1          
 Level type                                           1           2          
 Current x2APIC ID                                    00000004h   00000004h  
                                                                             
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Extended state enumeration and context management , CPUID function # 0000000Dh
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 Field                                                            Value      

 x87 ST0..7[79:0] state                                           1          
 SSE128 XMM0..15[127:0] state                                     1          
 AVX256 YMM0..15[255:128] state                                   1          
 MPX BNDREGS BND0..3[127:0] state                                 1          
 MPX BNDCSR state                                                 1          
 AVX512 OPMASK K0..7[63:0] state                                  0          
 AVX512 ZMM0..15[511:256] state                                   0          
 AVX512 ZMM16..31[511:0] state                                    0          
 IA32_XSS control                                                 0          
 PKRU control                                                     0          
 Maximum size for XSAVE/XRSTOR area, enabled features (bytes)     832        
 Maximum size for XSAVE/XRSTOR area, supported features (bytes)   1088       
 XCR0 bits [63-32]                                                00000000h  
                                                                             
 XSAVEOPT support                                                 1          
 XSAVEC and compact XRSTOR form support                           1          
 XGETBV function 1 support                                        1          
 XSAVES/XRSTORS and IA32_XSS                                      1          
 Size of XSAVE area for XCR0|IA32_XSS (bytes)                     00000340h  
 IA32_XSS MSR [31-00] bitmap                                      00000100h  
 IA32_XSS MSR [63-32] bitmap                                      00000000h  
                                                                             
 Base/Size                                                        576 , 256  
 Base/Size                                                        960 , 64   
 Base/Size                                                        1024 , 64  
                                                                             
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Platform quality of service (QoS) monitoring enumeration , CPUID function # 0000000Fh
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 Field                                                             Value  

 Maximum range (zero-based) of all types RMID                      0      
 R , Reserved                                                      0      
 L3 QoS , Supports L3 cache QoS monitoring                         0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
                                                                          
 Maximum range (zero-based) of RMID of this resource type          0      
 Conversion factor from IA32_QM_CTR to occupancy metric in bytes   0      
 L3 OM , Supports L3 occupancy monitoring                          0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
 R , Reserved                                                      0      
                                                                          
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Platform quality of service (QoS) enforcement enumeration , CPUID function # 00000010h
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 Field                                                          Value      

 R , Reserved                                                   0          
 L3 QoSE , L3 cache QoS enforcement                             0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
                                                                           
 Length of the capacity bit mask for the corresponding ResID    0          
 Bit-granular map of isolation/contention of allocation units   00000000h  
 Highest COS number supported for this ResID                    0          
 R , Reserved                                                   0          
 UCOS , Updates of COS should be infrequent                     0          
 CDPT , Code and data prioritization supported                  0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
 R , Reserved                                                   0          
                                                                           
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Software guard extensions (SGX) features and parameters , CPUID function # 00000012h
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 Field                                                           Value      

 MISCSELECT, reports the bit vector of supported ext. features   00000000h  
 Maximum enclave size when not in 64-bit mode (bytes)            1          
 Maximum enclave size in the 64-bit mode (bytes)                 1          
 SGX1 , Software Guard Extension instruction set #1 support      0          
 SGX2 , Software Guard Extension instruction set #2 support      0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
 R , Reserved                                                    0          
                                                                            
----------------------------------------------------------------------------------------------------
Processor trace enumeration , CPUID function # 00000014h
----------------------------------------------------------------------------------------------------

 Field                                                                 Value  

 FILTER , IA32_RTIT_CTL.CR3 filter can be set                          1      
 CPSB , Support configurable PSB and cycle-accurate mode               1      
 IPTSPT , IP, TraceStop filtering, preserv. PT MSR across warm reset   1      
 MTC , Sup. MTC timing packet and suppression COFI-based packets       1      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 ToPA , Tracing can be enabled with IA32_RTIT_CTL.ToPA=1               1      
 ToPA N , ToPA tables can hold any num. of output entries up to max.   1      
 SROS , Support of single-range output scheme                          1      
 TTS , Support of output to trace transport subsystem                  0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 R , Reserved                                                          0      
 LIP CS , Generated packets with IP payloads have LIP with CS base     0      
                                                                              
 Number of configurable address ranges for filtering                   2      
 Bitmap of supported MTC period encodings                              0249h  
 Bitmap of supported cycle threshold value encodings                   3FFFh  
 Bitmap of supported configurable PSB frequency encodings              003Fh  
                                                                              
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Time stamp counter and core crystal clock parameters , CPUID function # 00000015h
----------------------------------------------------------------------------------------------------

 Field                                              Value  

 Numerator for TSC/core crystal clock frequency     184    
 Denominator for TSC/core crystal clock frequency   2      
                                                           
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Processor clock frequency parameters , CPUID function # 00000016h
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 Field                            Value  

 Processor base frequency (MHz)   2200   
 Maximum frequency (MHz)          2400   
 Bus reference frequency (MHz)    100    
                                         
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Maximum extended function number , CPUID function # 80000000h
----------------------------------------------------------------------------------------------------

 Field                          Value, hex  

 Maximum extended CPUID level   80000008    
                                            
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Extended processor signature and extended features , CPUID function # 80000001h
----------------------------------------------------------------------------------------------------

 Field                                                    Value  

 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 SYS64 , SYSCALL/SYSRET in 64-bit mode (EFER/STAR MSRs)   1      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 XD , Execute disable bit, EFER.NXE                       1      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 1GBP , 1GB large pages                                   1      
 TSCP , RDTSCP and IA32_TSC_AUX                           1      
 R , Reserved                                             0      
 x64 , Intel 64 (EM64T) technlogy / AMD64 long mode       1      
 R , Reserved                                             0      
 R , Reserved                                             0      
 AHF64 , LAHF/SAHF available in 64-bit mode               1      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             1      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             1      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
 R , Reserved                                             0      
                                                                 
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Processor brand string , CPUID function # 80000002h
----------------------------------------------------------------------------------------------------

 Field             Value                                

 CPU name string   Genuine Intel(R) CPU 0000 @ 2.20GHz  
                                                        
----------------------------------------------------------------------------------------------------
Level 2 cache parameters , CPUID function # 80000006h
----------------------------------------------------------------------------------------------------

 Field                        Value      

 L2 cache size (KB)           256        
 L2 cache line size (bytes)   64         
 L2 associativity             6 (8-way)  
                                         
----------------------------------------------------------------------------------------------------
Invariant TSC support , CPUID function # 80000007h
----------------------------------------------------------------------------------------------------

 Field                   Value  

 Invariant TSC support   1      
                                
----------------------------------------------------------------------------------------------------
Physical and linear address size , CPUID function # 80000008h
----------------------------------------------------------------------------------------------------

 Field                           Value  

 Physical address width (bits)   39     
 Virtual address width (bits)    48     
                                        