Почему тайминги RAStoCAS Delay и RAS Precharge всегда выставляют одинаковыми? Например 2-2-2-6, 2,5-3-3-7, 3-4-4-8

но меня интересует почему многие люди (в том числе и производители) ставят эти два значения одинкаковыми?

а если как у тебя 7-3-2-2.5 то ты теряешь с пропускной способности где-то 100Mb/c

Did you know the Cylce time or (TRAS) should be equal to the sum of RAS2CAS + CAS + 2 cycles for maximum performance?
http://www.mushkin.com/mushkin/pop-up/latencies.htm

Memory, in many ways is like a book, you can only read after opening a book to a certain page and paragraph within that particular page. The RAS Pulse Width is the time until a page can be closed again. Therefore, just by definition, the minimum tRAS must be the RAS-to-CAS delay plus the read latency (CAS delay). That is fine for FPM and EDO memory with their single word data transfers. With SDRAM, memory controllers started to output a chain of four consecutive quadwords on every access. With DDR, that number has increased to eight quadwords that effectively are two consecutive bursts of four.

Now imagine someone closes the book you are reading from in the middle of a sentence. Right in your face! And does it over and again. This is what happens if tRAS is set too short. So here is the really simple calculation: The second burst of four has at least to be initiated and prefetched into the output buffers (like you get a glimpse at the headline in a book) before you can close the page without losing all information. That means that the minimum tRAS would be tRCD+CAS latency + 2 cycles (to output the first burst of four and make way for the second burst in the output buffers).

Any tRAS setting lower tRCD + CAS + 2 cycles will allow the memory controller to close the page “in your face!” over and again and that will cause a performance hit because of a truncated transfer that needs to be repeated. Along with those hassles comes the self-explanatory risk for data corruption. That one is not a real problem as long as the system is kept running but in case it is shut down and the memory content is written back to the hard disk drive, the consequences can be catastrophic. For the drive, that is.

ак почему ты это делаешь по таймингам а не по шине памяти.

А с чего ты взял, что их ВСЕГДА устанавливают одинаковыми? У меня память работает в состоянии 6-3-2-2