My take on this, as a software dev, it's not so much the latency increase of the consumer core Mesh vs Ringbus, that led to the regression in gaming performance. It's the changes to the L3 cache type & hierarchy. SkylakeX L3 is now essentially a victim cache like Zen, it's not an inclusive cache like prior Intel architectures. Victim cache actually makes a lot of sense for higher core counts as the cores can basically contribute to each other's performance with higher cache hits. But Intel sacrificed the per core L3 amount. For a victim cache to work well it needs more associations and much larger quantities. IMO, they could not make it larger as they are approaching a "too big a die.
It's actually worse than Zen (I'll explain) L3 design, but Intel is making up for it with brute clocks & larger L2. L3 typically have more cycles (slower latency vs L2 access), on Zen, AMD makes up for this by making it both large and shared with the other cores in the CCX. It's not 2MB per core, it's 8MB per 4 cores, all shared with enough associations for parallel read/write cycles. Zen's L3 acts as a core multiplier for cache hits, the more activity within that CCX, the higher the L3 hits will be because the byproduct cache data from each core gets shared with the others, any core that needs data, it checks that large L3 and hits it instead of tripping to RAM. Intel's Skylake X L3 is a victim cache that is crippled because they did not make it a shared cache with the other cores directly, but any access has to hop over the nodes on their Mesh. It's core specific, smaller and non-inclusive, a really bad combo for an L3. It's a compromised design focused for high core counts not meant to be great at gaming. They could have made it great for gaming too, but it would require more power and die size.