Notes from SemiAccurate's CC with Susquehanna this morning
Here are my hasty notes. Any of my comments are in brackets: [... ].

Susquehanna introduced Charlie as one who "breaks headlines", and whose blog has greater than 1M views per month.

He has previously provided private consultations for Wall Street.

Intel 10 nm has had issues, which Charlie pointed out starting in mid-2015. [I backed up the truck late that year].

Cannon Lake 10 nm, "launched" in 2017 with a single Lenovo China laptop, had single digit yields.

Charlie reported a "level of fear he had never seen" around then from Intel sources.

There were four to six distinct materials issues: Cobalt, SAQP, and COAG led the list on the technical side, but there were also management issues and a few smaller bugs.

The original plan was for four fabs to move to 10 nm.

3 out of the 4, including one in each of Israel, Arizona, and Oregon, will NOT move to 10 nm.

No info on what the 4th fab is doing, but at least 75% of the original 10 nm fab capacity is no longer there.

Cobalt: Below 50 nm, Copper doesn't scale well. Enter Cobalt, but it has a problem, in that it isn't consistent. Voids were the problem. INTC has probably fixed most of their Cobalt issues. [By cutting it back to only the largest metal layers?].

SQ question: Can INTC pull a rabbit out of their hat? No INTC "rabbit out of a hat" is likely, TSMC and Samsung are ahead on process.

TSMC is already making tens of millions of chips a quarter on 7 nm, a close match to INTC 10 nm on density. [INTC has probably degraded their original 10 nm in order to make working products].

Some foundry smartphone chips already use Cobalt, definitely Huawei. [I think that Intel unwisely decided to use Co for finer metal layers].

The SAQP (Single Aligned Quad Patterning) issue has largely been solved, and is in good shape.

COAG (Contact Over Active Gate) was to have saved INTC 10% in area. It completely failed, impacting integrated graphics. This is why the Q4 2017 10 nm Canon Lake had no iGPU.

From INTC's 2017 Process Day slide, it was clear from the start that both 10 nm and 10 nm+ would start out behind 14 nm.

14 nm hasn't been standing still since then, and 10 nm has stalled.

Performance matters more than power, and caps ASPs.

10 nm is slower, and its yields are < 50% that of 14 nm.

The recently leaked Dell roadmaps confirm that the INTC 2017 claim that 10 nm and 10nm+ processes will be behind on performance compared to 14 nm. [Especially with an arbitrary number of "+" signs].

INTC will have very little capacity on 10 nm, due to only having 1 or at most 1.5 fabs on that process.

SQ described 10 nm as a "slow rollout, paper launch". [I agree]

In 2021, Cooper Lake will be 14 nm [Charlie mispoke when he mentioned 10 nm; Cooper Lake is 14 nm].

Ice Lake 10 nm will only be the low performance end of the stack. It will also come in 14 nm variants.

High core count and performance as well as AI with Bfloat 16 will remain at 14 nm.

Charlie defines the current INTC Cascade Lake as unity (1.0x); previous gen at 0.93.

Amd's Naples (launched in 2017) is 0.87.

INTC's gain over the last 18 months has been only ~ 6%.

In mid 2020, with Cooper Lake 14 nm, they get to 1.3.

INTC has "no chance".

AMD's Rome has already been shipping to big customers, and will launch in "a few weeks".

Rome delivers a 1.6x performance delta over INTC's current and for the next year Cascade Lake.

INTC's Ice Lake in the second half of 2020 will deliver a 1.5x gain.

But it will be competing then with AMD's "Milan", which raises the bar significantly: ~ 2X Cascade Lake.

AMD will have a 50 to 60% server CPU performance advantage until at least late 2021.

Questioned about INTC 14 nm shortages, Charlie mentions (previously behind the paywall) that this was driven by massive hits to server customers from Spectre and Meltdown security flaws, which drove volume buys to restore capacity [China buys ahead of tariffs in Intel speak].

The other driver was the average core count required to compete with AMD.

INTC had to to double their core count and hence silicon area at no increase in ASP to compte. With only one quarter the fab capacity at 10 nm, that isn't happening.

Charlie can't confirm if Ryzen Gen 3 will launch with 16 cores.

INTC's Fab 28 in Israel has been back ported to 14 nm.

Intel is adding new fabs, but they have a long time to bring up.

AMD Milan will have an amazing 15 chiplets.

AMD is pushing chiplets very hard.

Yield is inversely proportional to die size, but not in a linear way.

With higher yields and lower costs, AMD can clobber Intel with EPYC.

Milan, think Rome with six more small chiplets, saves tremendous amounts of money, and is faster.

Naples is 219 mm^2 x 4.

Rome is ~ 85 mm^2 x 8.

That is smaller than Apple's 7 nm iPhone chip (hence better yields), which TSMC is already making tens of millions of a quarter.

With Rome's memory I/O die, the latency hit of chiplets will now be minimal.

AMD is only 10 to 15% behind INTC now, on a poorer 14 nm process.

Rome really changes the architecture; AMD "did it right".

What about Intel's custom SKU capability? Well, they really only have three dies for servers. The wide range of custom SKU's are nothing more than charging some customers more for crippling less. A 10% custom SKU can't compete against a 60% advantage.

"INTC is still going to lose badly".

What about cost? Naples caps at $4.5k. Skylake is capped at $13k. Cascade Lake caps at $18K.

Are a few added features worth 4x the cost for significantly lower performance? [No.]

Could INTC go fab lite? That would add less value than people expect, but Keller and Raja could make it possible.

All INTC custom foundry customers have bailed, including Cisco, Panasonic, and LG. The entire INTC custom foundry effort was a flaming disaster.

This radically decreases the value of any attempt to spin off their fabs, as AMD successfully did in 2007.

INTC has used TSMC before, on the 65 and 40 nm nodes. New reveal: this was done to strangle competitors who depended on that fab capacity.

INTC going fabless in the future is possible but not probable. [Not to mention the insanely high capital write-downs that this would require].

Why didn't Google mention using Rome on their Stadia Day? This was part one of a two-part question, and with time running out or Charlie forgetting, they didn't circle back. [My take: It's Rome for the Stadia CPUs, but Google couldn't announce this before Rome launches. Note that on slide #12 on the recently added AMD IR May 2019 Investor Presentation (at http://ir.amd.com), under the Cloud Gaming section, there is an EPYC processor. You get the drift...]

Sunny Lake gains are much less than 25%, and are already included in Charlie's multiples.

Optane "is OK", but at $7K for the largest, pricey.

In single threaded applications, INTC is likely to maintain a slight lead, almost close to zero.

But AMD will have double the core count.

AI re QCOM and NVDA. Training is massively compute intensive. Inference is easy, QCOM is solely inference. NVDA and INTC dominate training.