Всем привет.
Хочу расказать вам (не без определенного денежного интереса), что есть путь взять практически любой ксеон (1333) и поставить его на плату LGA775.
Главное чтобы она поддерживала квадкоры (смотрим в спецификациях).
Все что нужно сделать это чуток подрезать плату как рассказано тут:

https://www.youtube.com/watch?v=kPBbpSgUXkw
И сделать самому или купить переходник, который перекидывает два пина на процессоре:
https://www.youtube.com/watch?v=NX48ERjMWws
Результат выглядит вот так:
https://www.youtube.com/watch?v=T9mA7J_YSZs
Весьма и весьма впечатляет.
Итого за 60$ можно заиметь неплохой Х5460 на вашей плате с ЛГА775 ))
Лично у меня стоит L5430.
У меня он встал без всяких прописываний кодов в биосе и прочих проблем.
Я прогнал инстеловский тест для процессоров просто убедиться что все что есть работеает ОК.
У меня есть куча таких адаптеров, которые я продаю на ибее (у меня там такой же ник как и на форуме) а так же могу продать за вебмани в России.
Письмо с адаптером посылаю из Израиля. До Москвы доходит за неделю (вроде как), ну а если вы живете где-то подальше, то дольше конечно.

Повторяю - адаптер не обязательно покупать, можно сделать и самому.

За адаптер + пересылку прошу 10$.

Интересно будет послушать мнение людей по поводу разгона таких процессоров (стоит ли вообще).
Спасибо.

Добавлено спустя 8 минут 4 секунды:
результаты Coreinfo на Windows 7 x86
C:\1>Coreinfo

Coreinfo v3.31 - Dump information on system CPU and memory topology
Copyright (C) 2008-2014 Mark Russinovich
Sysinternals - http://www.sysinternals.com

Intel(R) Xeon(R) CPU X5460 @ 3.16GHz
x86 Family 6 Model 23 Stepping 10, GenuineIntel
Microcode signature: 00000A0B
HTT * Hyperthreading enabled
HYPERVISOR - Hypervisor is present
VMX * Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
X64 * Supports 64-bit mode

SMX - Supports Intel trusted execution
SKINIT - Supports AMD SKINIT

NX * Supports no-execute page protection
SMEP - Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB - Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE - Supports direct GS/FS base access

FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4a - Supports Streaming SIMDR Extensions 4a
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 - Supports Streaming SIMD Extensions 4.2

AES - Supports AES extensions
AVX - Supports AVX intruction extensions
FMA - Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE * Supports XSAVE/XRSTOR instructions
OSXSAVE - Supports XSETBV/XGETBV instructions
RDRAND - Supports RDRAND instruction
RDSEED - Supports RDSEED instruction

CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 - Supports bit manipulation extensions 1
BMI2 - Supports bit manipulation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA * Supports prefetch from memory-mapped device
F16C - Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR * Supports MONITOR and MWAIT instructions
MOVBE - Supports MOVBE instruction
ERMSB - Supports Enhanced REP MOVSB/STOSB
PCLMULDQ - Supports PCLMULDQ instruction
POPCNT - Supports POPCNT instruction
LZCNT - Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions

DE * Supports I/O breakpoints including CR4.DE
DTES64 * Can write history of 64-bit branch addresses
DS * Implements memory-resident debug buffer
DS-CPL * Supports Debug Store feature with CPL
PCID - Supports PCIDs and settable CR4.PCIDE
INVPCID - Supports INVPCID instruction
PDCM * Supports Performance Capabilities MSR
RDTSCP - Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
TSC-INVARIANT - TSC runs at constant rate
xTPR * Supports disabling task priority messages

EIST * Supports Enhanced Intel Speedstep
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 * Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC

CNXT-ID - L1 data cache mode adaptive or BIOS

MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin

PSN - Implements 96-bit processor serial number

PREFETCHW * Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 0000000D (Basic), 80000008 (Extended).

Logical to Physical Processor Map:
*--- Physical Processor 0
-*-- Physical Processor 1
--*- Physical Processor 2
---* Physical Processor 3

Logical Processor to Socket Map:
**** Socket 0

Logical Processor to NUMA Node Map:
**** NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
*--- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
*--- Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
-*-- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
-*-- Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--*- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
--*- Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
-**- Unified Cache 0, Level 2, 6 MB, Assoc 24, LineSize 64
---* Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
---* Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
*--* Unified Cache 1, Level 2, 6 MB, Assoc 24, LineSize 64

Logical Processor to Group Map:
**** Group 0

C:\1>

Intel(R) LINPACK 64-bit data - LinX v0.7.0

Current date/time: Sat May 20 14:23:21 2017

CPU frequency: 3.513 GHz
Number of CPUs: 1
Number of cores: 4
Number of threads: 4

Parameters are set to:

Number of tests: 1

Number of equations to solve (problem size) : 23118
Leading dimension of array : 23128
Number of trials to run : 3
Data alignment value (in Kbytes) : 4
Maximum memory requested that can be used=4277851488, at the size=23118

=================== Timing linear equation system solver ===================

Size LDA Align. Time(s) GFlops Residual Residual(norm) Check
23118 23128 4 195.170 42.2088 5.908415e-10 3.926272e-02 pass
23118 23128 4 177.674 46.3651 5.908415e-10 3.926272e-02 pass
23118 23128 4 179.561 45.8779 5.908415e-10 3.926272e-02 pass

Performance Summary (GFlops)

Size LDA Align. Average Maximal
23118 23128 4 44.8172 46.3651

Residual checks PASSED

End of tests