tried increasing SA/MC with 0.05v and it just made it worse TM5 doesn't survive 2 min, also tried 1.22SA/1.5MC and same thing, reverted back to most stable settings again, and it also doesn't survive 2 min of TM5."(С)
This is what VDDQ Training on "off" does 🤭
If you reverted and voltages don't work = your voltages were never correct.
Your stability was based on dynamic training ~ meaning it will lose stability whenever it wants.
We are forced to get voltages now correct.
It can be helpful to lower clock, adjust CKE, XP, CPDED back down ~ use tRFC mini to prevent rounding issues
And verify if it remains unstable.
VDD2_CPU (MC) and SA are not corrected directly.
Indirectly SA messes with MC-Link voltage
Also messes with VDDQ_CPU (IVR TX) voltage.
But no direct connection. Side influence
Meaning, no need to change them together.
Pick an SA bellow 1.25v, above 1.15v
// correct decision depends on how good [low voltage] V/F curve is = how less-leaky sample is
Then same goes for VDD2_CPU (MC-Link). 8400MT/s is somewhere between 1.38-1.44v.
And once you got this, you find correct distance of VDDQ to VDDQ
24gb likely is between 90-180mV. Most likely between 105-150mV
16gb likely is between 120-255mV. Most likely between 180-225mV
^ for current (Dec-January) Bios RTT & Groups Tuning
We target SA between 1.14-1.2v for 8400.
Most optimally bellow 1.18v
Your sample targets SA near 1.16-1.18v.
SA needs only change , if margins get smaller and smaller.
Else SA needs no change if CPU has headroom.
SA (side-influence !) Processor-ODT change. Processor-ODT change is hidden.
ODT change herby messes with all voltages. So SA side-influence all CPU-Side voltages.
Real IMC supply can not be changed by Overclockers. Margins for IMC are side-influence change by VID of sample and (Bios) ODT defined ~ for sample.
Any PLL used
Any CPU_AUX increase.
Any VPP_MEM increase.
Any slopes. Will mess with min/max ~ target voltage
No PLLs for daily conditions.
Only for ice cold conditions.
Only if BoardPCB is subzero or past 8600MT/s.
Gear 4 is no exception. UCLK is 1/4th. No PLL requirement

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