Чтение с модуля памяти у DDR4 происходит блоками. Минимальный блок сейчас составляет 64 байта, что связано с размером строки кэша у процессора. Этот блок может считываться как с одного банка, так и с разных.
tRAS=tRCD+tRTP (при считывании 8 байт с одного банка)
tRAS=tRCD+tRTP+4 (при считывании 16 байт с одного банка)
tRAS=tRCD+tRTP+8 (считывание 24 байт - маловероятно)
tRAS=tRCD+tRTP+12 (при считывании 32 байт с одного банка). Самый верный выбор для DDR4!
tRAS=tRCD+tRTP+16 (считывание 40 байт - маловероятно)
tRAS=tRCD+tRTP+20 (считывание 48 байт - маловероятно)
tRAS=tRCD+tRTP+24 (считывание 56 байт - маловероятно)
tRAS=tRCD+tRTP+28 (при считывании 64 байт с одного банка)
Для DDR4 оптимальным выбором является 4-й или последний вариант.
Но если выставить tRAS меньше, то ничего трагичного не произойдет, так как джедек придумала предохранитель (tRTP), поэтому можно не заморачиваться и выставлять минимальный tRAS (=tRCD+tRTP).

SA- безопасный уровень (по данным MSI) 1.35, растет от частоты памяти и зависит от подключенной периферии к PCIE, чем больше скорость видеокарты и NVME-диска, тем выше нужно напряжение.
IO (для Z590 =IO2, а просто IO можно оставлять в авто, для Z690=IVR DDQ)- обычно хорошо работает если на 50 мВ ниже SA, но чем ниже, тем лучше, стараться максимально снижать.
Тоже растет с ростом частоты памяти.
Для ориентира при настройке всегда рекомендую глянуть, что за напряжения SA и IO выставляет материнка в авто.

Универсальный гайд.
0. Устраните любые потенциальные проблемы с другим железом. Снимите разгон с видеокарты, снизьте частоту цп на 300 с сохранением напряжения. Не забудьте вернуть RTL в авто если сейчас не авто.
1. Крутим очень короткий мемтест, то есть если минуту живёт сразу снижать тайминг дальше. Ищите не стабильность, а явно сбойное значение тайминга, запишите его - пригодится. Гораздо проще найти явно нерабочее значение и от него плясать чем пытаться ловить нестабильность часами. Это также помогает диагностировать сбойные тайминги на ранее "стабильной памяти".
Не пытайтесь найти предельные значение сразу. Сначала скрутите до +2 от минимально стабильного. Многие тайминги идут параллельно поэтому бессмысленно пытаться скрутить до упора с первого прохода.
CR выставить на 2 если стоит 1. В самом конце можно попробовать скинуть до 1. 3 Ставить только на очень большую частоту или если по другому ну совсем никак.

Начните с RCD, CL. Не обязательно должны быть одинаковыми, обычно CL идёт меньше чем RCD.
RAS сразу пробуйте как RCD+CL+4, до этого значения от него существенная разница, дальше меньше.
CWL<=CL. Допустимые значения 9,10,11,12,14,16,18,20.
RP можете выставить по RCD, если пойдёт меньше - тоже неплохо, не уверен правда насчёт смысла.
RTP без формул. Если не идёт вниз можно попробовать поднять чуть чуть RP. В DDR4 явно связан с WR соотношением 2 к 1 (например WR20\RTP10), физически хранится одно значения и в зависимости от операции интерпретируется.
Скрутите FAW до 16(так и оставьте если работает). С таким FAW скручивайте RRD(оба, L обычно больше чем S), возможно поедут на 4 оба. Если до 4 не удалось спустить поднимите FAW до уровня RRDL*4 и попробуйте ещё, хотя это скорее всего уже почти предел.
Обычно L>=S. L - SG(Same Group). S - DG(Different Group) Напр. RRD_L>=RRD_S.
CKE=5
СCDL>=4
RDRD_DD и прочие подобные можно проигнорировать если у вас нет двух планок на один канал (4 планки). DD-Different Dimm. Тоже самое с DR-Different Rank если у вас одноранговая память.
RDWR_SG(DG) и подобные сочетания скручивайте до минимальных рабочих, потом накиньте сверху +2. Как уже отметил обычно SG>=DG.
WTR не трогайте он сам спустится когда будете скидывать WRRD_SG(DG) и прочие подобные. Если сам меньше не стал тогда руками скидывать.
WR снижать через WRPRE если есть. Если нет или не снижает WR, То скрутите его скажем до 12 или +4 от рабочего, потом дожмёте если не лень будет.
RFC явных формул нет, крутить после всего списка сверху. Не пытайтесь найти его минимальное значение если не хотите чтобы память начинала сыпать ошибками от любого чиха. найдите пограничное со стабильностью значение и накиньте сверху 20 или сразу 40. Может реагировать на RAS+RP, RRD, FAW, причём в обе стороны (то есть может "сломаться" если задрать названные), а может и не реагировать...
REFi больше лучше. Связан с RFC. REFI сколько память "работает" - RFC сколько "отдыхает". Оба тайминга лучше не пытаться найти предельное значение.Заметно реагируют на температуру.
Многие тайминги отзываются и на температуру и на напряжение. Поскольку напряжение может как позволить снизить тайминг, так и увеличить температуру, то середину можно искать очень долго, поэтому лучше бы вовремя остановится.
Тестируйте тщательно с перезагрузками, сном, холодным стартом.
RTL и IOL вам кто-то другой пусть советует как настраивать, от них у меня голова болеть начинает...

Актуальные (последние) версии:
TableDRAMIntel(simple3nov2020+simple12oct2020+обычная)
http://bit.ly/3rTIBLv
http://bit.ly/3nWJlxB
http://bit.ly/32WnkTU
Conf tm5(slight+uni@LMHz+extreme+absolut)
http://bit.ly/2Oe8R00 - суперлайт
http://bit.ly/2H9jIZH - универсальный
http://bit.ly/2MUvl6n - экстремальный
http://bit.ly/3D9TUnD - абсолют
http://bit.ly/3STH2wx - новый для интела и DDR5
http://bit.ly/3wedj8U - новый для Ryzen3D и DDR5
Тяжелый
http://bit.ly/35eKfeJ

VDDDQ=1.5 V max по Jedec
VrefCA=0.6xVDDDQ=0.9 V (max по Jedec), в даташите контроллера интел тоже разрешено максимальное vrefca=0.6xVdddq.
То есть при обычной настройке биоса, когда VrefCA=0.5xVDDDQ, VDRAM<=1.8 V, чтобы уложиться в нормы по Jedec.
А если при этом в биосе настроить vrefca=0.49xvdddq (разрешено по Jedec), то безопасное Vdram может быть еще выше=1.837 V.
Вывод: для контроллера процессора напряжение на память <=1.8 V неопасно

https://forums.overclockers.ru/viewtopic.php?p=17484594#p17484594
На OCN есть методика их подбора с помощью Passmark memtest86, использовать только 8-й тест.

Below are the typical tRFC in ns for the common ICs:
IC tRFC (ns)
Hynix 8Gb AFR 260 - 280
Hynix 8Gb CJR 260 - 280
Hynix 8Gb DJR 260 - 280
Micron 8Gb Rev. E 280 - 310
Micron 16Gb Rev. B 290 - 310
Samsung 8Gb B-Die 120 - 180
Samsung 8Gb C-Die 300 - 340

#77
#77
#77
Чем выше вы в вертикальном столбце, тем удачнее планки.
Чем интенсивнее цвет, тем выше статистический процент (данные старые,теперь удачнее чипы выходят)
На 1 таблице все,что выше красной линии - суперотборники.

1.Поднять напряжения на VCCSA и VCCIO.
2.Включить в биосе Round Trip Latency.
3.Для гигабайтов - memory enchancement=normal.

https://docs.google.com/document/d/15qsrwUxGbKtqjeyEhmCear2kN9hCt2noKK5z14Webhg/edit?usp=sharing
https://docs.google.com/document/u/0/d/1QacU405kVV10-qBdrqQKOY0v-FKlBFpLcEDn0QpriSE/mobilebasic на русском
Мобильная версия
https://docs.google.com/document/u/0/d/15qsrwUxGbKtqjeyEhmCear2kN9hCt2noKK5z14Webhg/mobilebasic

GSAT- https://drive.google.com/file/d/1iCj0-jQIXIlo_Zvm5jO949ZH9fClTNF3/edit
для длинных тестов добавил параметр "--pause_delay" чтоб периодически не отключались потоки

[2022/05/03 16:37:20]
Ai Overclock Tuner [Manual]
BCLK Frequency [100.0000]
ASUS MultiCore Enhancement [Disabled]
SVID Behavior [Worst-Case Scenario]
AVX Instruction Core Ratio Negative Offset [0]
CPU Core Ratio [Sync All Cores]
1-Core Ratio Limit [47]
2-Core Ratio Limit [47]
3-Core Ratio Limit [47]
4-Core Ratio Limit [47]
5-Core Ratio Limit [47]
6-Core Ratio Limit [47]
7-Core Ratio Limit [47]
8-Core Ratio Limit [47]
BCLK Frequency : DRAM Frequency Ratio [100:133]
DRAM Odd Ratio Mode [Disabled]
DRAM Frequency [DDR4-4000MHz]
Xtreme Tweaking [Enabled]
TPU [Keep Current Settings]
CPU SVID Support [Enabled]
CPU Core/Cache Current Limit Max. [255.75]
Ring Down Bin [Disabled]
Min. CPU Cache Ratio [Auto]
Max CPU Cache Ratio [43]
BCLK Aware Adaptive Voltage [Auto]
CPU Core/Cache Voltage [Offset Mode]
- Offset Mode Sign [-]
- CPU Core Voltage Offset [0.120]
DRAM Voltage [1.3600]
CPU VCCIO Voltage [1.11250]
CPU System Agent Voltage [1.12500]
PLL Termination Voltage [Auto]
PCH Core Voltage [Auto]
CPU Standby Voltage [Auto]
DRAM CTRL REF Voltage on CHA [Auto]
DRAM CTRL REF Voltage on CHB [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL0 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL1 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL2 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL3 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL4 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL5 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL6 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank0 BL7 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL0 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL1 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL2 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL3 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL4 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL5 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL6 [Auto]
DRAM DATA REF Voltage on CHA DIMM0 Rank1 BL7 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL0 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL1 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL2 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL3 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL4 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL5 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL6 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank0 BL7 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL0 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL1 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL2 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL3 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL4 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL5 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL6 [Auto]
DRAM DATA REF Voltage on CHA DIMM1 Rank1 BL7 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL0 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL1 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL2 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL3 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL4 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL5 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL6 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank0 BL7 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL0 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL1 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL2 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL3 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL4 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL5 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL6 [Auto]
DRAM DATA REF Voltage on CHB DIMM0 Rank1 BL7 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL0 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL1 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL2 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL3 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL4 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL5 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL6 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank0 BL7 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL0 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL1 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL2 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL3 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL4 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL5 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL6 [Auto]
DRAM DATA REF Voltage on CHB DIMM1 Rank1 BL7 [Auto]
Realtime Memory Timing [Disabled]
FCLK Frequency for Early Power On [Auto]
Initial BCLK Frequency [Auto]
BCLK Amplitude [Auto]
BCLK Slew Rate [Auto]
BCLK Spread Spectrum [Disabled]
BCLK Frequency Slew Rate [Auto]
DRAM VTT Voltage [Auto]
VPPDDR Voltage [Auto]
DMI Voltage [Auto]
Core PLL Voltage [Auto]
Internal PLL Voltage [Auto]
GT PLL Voltage [Auto]
Ring PLL Voltage [Auto]
System Agent PLL Voltage [Auto]
Memory Controller PLL Voltage [Auto]
PLL Bandwidth [Auto]
Eventual DRAM Voltage [Auto]
Eventual CPU Standby Voltage [Auto]
Eventual PLL Termination Voltage [Auto]
Eventual DMI Voltage [Auto]
Maximus Tweak [Mode 2]
DRAM CAS# Latency [16]
DRAM RAS# to CAS# Delay [18]
DRAM RAS# ACT Time [36]
DRAM Command Rate [2N]
DRAM RAS# to RAS# Delay L [6]
DRAM RAS# to RAS# Delay S [4]
DRAM REF Cycle Time [592]
DRAM Refresh Interval [65024]
DRAM WRITE Recovery Time [16]
DRAM READ to PRE Time [8]
DRAM FOUR ACT WIN Time [16]
DRAM WRITE to READ Delay [Auto]
DRAM WRITE to READ Delay L [8]
DRAM WRITE to READ Delay S [4]
DRAM CKE Minimum Pulse Width [8]
DRAM Write Latency [16]
tRDRD_sg [7]
tRDRD_dg [4]
tRDWR_sg [12]
tRDWR_dg [12]
tWRWR_sg [7]
tWRWR_dg [4]
tWRRD_sg [30]
tWRRD_dg [26]
tRDRD_dr [0]
tRDRD_dd [0]
tRDWR_dr [0]
tRDWR_dd [0]
tWRWR_dr [0]
tWRWR_dd [0]
tWRRD_dr [0]
tWRRD_dd [0]
TWRPRE [36]
TRDPRE [8]
tREFIX9 [127]
OREF_RI [0]
MRC Fast Boot [Enabled]
DRAM CLK Period [Auto]
Memory Scrambler [Enabled]
Channel A DIMM Control [Enabled]
Channel B DIMM Control [Enabled]
MCH Full Check [Enabled]
Mem Over Clock Fail Count [Auto]
Training Profile [Auto]
DLLBwEn [Auto]
DRAM SPD Write [Disabled]
XTU Setting [Auto]
DRAM RTL INIT value [Auto]
DRAM RTL (CHA DIMM0 Rank0) [60]
DRAM RTL (CHA DIMM0 Rank1) [0]
DRAM RTL (CHA DIMM1 Rank0) [0]
DRAM RTL (CHA DIMM1 Rank1) [0]
DRAM RTL (CHB DIMM0 Rank0) [61]
DRAM RTL (CHB DIMM0 Rank1) [0]
DRAM RTL (CHB DIMM1 Rank0) [0]
DRAM RTL (CHB DIMM1 Rank1) [0]
DRAM IOL (CHA DIMM0 Rank0) [6]
DRAM IOL (CHA DIMM0 Rank1) [0]
DRAM IOL (CHA DIMM1 Rank0) [0]
DRAM IOL (CHA DIMM1 Rank1) [0]
DRAM IOL (CHB DIMM0 Rank0) [6]
DRAM IOL (CHB DIMM0 Rank1) [0]
DRAM IOL (CHB DIMM1 Rank0) [0]
DRAM IOL (CHB DIMM1 Rank1) [0]
CHA IO_Latency_offset [21]
CHB IO_Latency_offset [21]
CHA RFR delay [14]
CHB RFR delay [14]
ODT RTT WR (CHA) [80 DRAM Clock]
ODT RTT PARK (CHA) [48 DRAM Clock]
ODT RTT NOM (CHA) [48 DRAM Clock]
ODT RTT WR (CHB) [80 DRAM Clock]
ODT RTT PARK (CHB) [48 DRAM Clock]
ODT RTT NOM (CHB) [48 DRAM Clock]
ODT_READ_DURATION [Auto]
ODT_READ_DELAY [Auto]
ODT_WRITE_DURATION [Auto]
ODT_WRITE_DELAY [Auto]
Data Rising Slope [Auto]
Data Rising Slope Offset [Auto]
Cmd Rising Slope [Auto]
Cmd Rising Slope Offset [Auto]
Ctl Rising Slope [Auto]
Ctl Rising Slope Offset [Auto]
Clk Rising Slope [Auto]
Clk Rising Slope Offset [Auto]
Data Falling Slope [Auto]
Data Falling Slope Offset [Auto]
Cmd Falling Slope [Auto]
Cmd Falling Slope Offset [Auto]
Ctl Falling Slope [Auto]
Ctl Falling Slope Offset [Auto]
Clk Falling Slope [Auto]
Clk Falling Slope Offset [Auto]
CPU Load-line Calibration [Level 1]
CPU Current Capability [140%]
CPU VRM Switching Frequency [Auto]
Active Frequency Mode [Enabled]
CPU Power Duty Control [T.Probe]
CPU Power Phase Control [Extreme]
CPU Power Thermal Control [120]
CPU VRM Thermal Control [Auto]
DRAM Current Capability [130%]
DRAM Switching Frequency [Auto]
CPU Core/Cache Boot Voltage [Auto]
DMI Boot Voltage [Auto]
Core PLL Boot Voltage [Auto]
CPU System Agent Boot Voltage [Auto]
CPU VCCIO Boot Voltage [Auto]
PLL Termination Boot voltage [Auto]
CPU Standby Boot Voltage [Auto]
Intel(R) SpeedStep(tm) [Disabled]
Turbo Mode [Enabled]
Long Duration Package Power Limit [4095]
Package Power Time Window [127]
Short Duration Package Power Limit [4095]
IA AC Load Line [Auto]
IA DC Load Line [Auto]
TVB Voltage Optimizations [Disabled]
Hyper-Threading [Enabled]
Thermal Monitor [Enabled]
Maximum CPU Core Temperature [Auto]
Active Processor Cores [All]
Intel Virtualization Technology [Disabled]
Hardware Prefetcher [Enabled]
Adjacent Cache Line Prefetch [Enabled]
Boot performance mode [Auto]
SW Guard Extensions (SGX) [Disabled]
Tcc Offset Time Window [Auto]
Execute Disable Bit [Disabled]
SMM Code Access Check [Enabled]
SMM Use Delay Indication [Enabled]
SMM Use Block Indication [Enabled]
Intel(R) SpeedStep(tm) [Disabled]
Turbo Mode [Enabled]
CPU C-states [Disabled]
CFG Lock [Disabled]
Intel(R) Speed Shift Technology [Enabled]
Number of P states [0]
Acoustic Noise Mitigation [Disabled]
Disable Fast PKG C State Ramp for IA Domain [FALSE]
Slow Slew Rate for IA Domain [Fast/2]
Disable Fast PKG C State Ramp for GT Domain [FALSE]
Slow Slew Rate for GT Domain [Fast/2]
Disable Fast PKG C State Ramp for SA Domain [FALSE]
Slow Slew Rate for SA Domain [Fast/2]
Configurable TDP Boot Mode [Nominal]
Configurable TDP Lock [Disabled]
CTDP BIOS control [Disabled]
Power Limit 1 [0]
Power Limit 2 [0]
Power Limit 1 Time Window [0]
ConfigTDP Turbo Activation Ratio [0]
Overclocking Lock [Disabled]
PCI Express Native Power Management [Disabled]
PCH DMI ASPM [Disabled]
ASPM [Disabled]
DMI Link ASPM Control [Disabled]
PEG - ASPM [Disabled]
PTID Support [Enabled]
PECI Access Method [Direct I/O]
PCI Express Native Power Management [Disabled]
BDAT ACPI Table Support [Disabled]
Wake system from S5 [Disabled]
ACPI Debug [Disabled]
Low Power S0 Idle Capability [Disabled]
Lpit Recidency Counter [SLP S0]
PCI Delay Optimization [Disabled]
ZpODD Support [Disabled]
Type C Support [Enabled]
PEP CPU [Enabled]
PEP Graphics [Enabled]
PEP ISP [Disabled]
PEP SATA Controller [Enabled]
PEP RAID VOL0 [Disabled]
PEP SATA PORT0 [Disabled]
PEP SATA PORT1 [Disabled]
PEP SATA PORT2 [Disabled]
PEP SATA PORT3 [Disabled]
PEP SATA PORT4 [Disabled]
PEP SATA PORT5 [Disabled]
PEP SATA NVM1 [Disabled]
PEP SATA NVM2 [Disabled]
PEP SATA NVM3 [Disabled]
PEP UART [Enabled]
PEP I2C0 [Enabled]
PEP I2C1 [Enabled]
PEP I2C2 [Enabled]
PEP I2C3 [Enabled]
PEP I2C4 [Enabled]
PEP I2C5 [Enabled]
PEP SPI [Enabled]
PEP XHCI [Enabled]
PEP Audio [Enabled]
PEP EMMC [Enabled]
PEP SDXC [Enabled]
VT-d [Disabled]
Primary Display [Auto]
iGPU Multi-Monitor [Disabled]
DMI Max Link Speed [Gen3]
PCIEX16/X8_1 Link Speed [Gen3]
PCIEX8/X4_3 Link Speed [Auto]
PCIEX4_2 Link Speed [Auto]
PCIe Spread Spectrum Clocking [Disabled]
IOAPIC 24-119 Entries [Enabled]
PCIe Speed [Gen3]
SATA Controller(s) [Disabled]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 0 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 1 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 2 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 3 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 4 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 5 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Port 6 [Enabled]
Hot Plug [Disabled]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 6 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
Port 7 [Enabled]
Hot Plug [Disabled]
Spin Up Device [Disabled]
SATA Device Type [Hard Disk Drive]
Topology [Unknown]
SATA Port 7 DevSlp [Disabled]
DITO Configuration [Disabled]
DITO Value [625]
DM Value [15]
PCI Express Root Port 1 [Enabled]
Topology [Unknown]
ASPM [Disabled]
L1 Substates [Disabled]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE1 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE1 LTR Lock [Disabled]
PCIE1 CLKREQ Mapping Override [Default]
PCI Express Root Port 2 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE2 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE2 LTR Lock [Disabled]
PCIE2 CLKREQ Mapping Override [Default]
PCI Express Root Port 3 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE3 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE3 LTR Lock [Disabled]
PCIE3 CLKREQ Mapping Override [Default]
PCI Express Root Port 4 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE4 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE4 LTR Lock [Disabled]
PCIE4 CLKREQ Mapping Override [Default]
PCI Express Root Port 5 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE5 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE5 LTR Lock [Disabled]
PCIE5 CLKREQ Mapping Override [Default]
PCI Express Root Port 6 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE6 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE6 LTR Lock [Disabled]
PCIE6 CLKREQ Mapping Override [Default]
PCI Express Root Port 7 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [7]
Reserved Memory [17]
Reserved I/O [16]
PCH PCIE7 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE7 LTR Lock [Disabled]
PCIE7 CLKREQ Mapping Override [Default]
PCI Express Root Port 8 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [7]
Reserved Memory [17]
Reserved I/O [8]
PCH PCIE8 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE8 LTR Lock [Disabled]
PCIE8 CLKREQ Mapping Override [Default]
PCI Express Root Port 9 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE9 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE9 LTR Lock [Disabled]
PCIE9 CLKREQ Mapping Override [Default]
PCI Express Root Port 10 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE10 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE10 LTR Lock [Disabled]
PCIE10 CLKREQ Mapping Override [Default]
PCI Express Root Port 11 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE11 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE11 LTR Lock [Disabled]
PCIE11 CLKREQ Mapping Override [Default]
PCI Express Root Port 12 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE12 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE12 LTR Lock [Disabled]
PCIE12 CLKREQ Mapping Override [Default]
PCI Express Root Port 13 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE13 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE13 LTR Lock [Disabled]
PCIE13 CLKREQ Mapping Override [Default]
PCI Express Root Port 14 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE14 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE14 LTR Lock [Disabled]
PCIE14 CLKREQ Mapping Override [Default]
PCI Express Root Port 15 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE15 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE15 LTR Lock [Disabled]
PCIE15 CLKREQ Mapping Override [Default]
PCI Express Root Port 16 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE16 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE16 LTR Lock [Disabled]
PCIE16 CLKREQ Mapping Override [Default]
PCI Express Root Port 17 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE17 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE17 LTR Lock [Disabled]
PCIE17 CLKREQ Mapping Override [Default]
PCI Express Root Port 18 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE18 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE18 LTR Lock [Disabled]
PCIE18 CLKREQ Mapping Override [Default]
PCI Express Root Port 19 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE19 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE19 LTR Lock [Disabled]
PCIE19 CLKREQ Mapping Override [Default]
PCI Express Root Port 20 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE20 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE20 LTR Lock [Disabled]
PCIE20 CLKREQ Mapping Override [Default]
PCI Express Root Port 21 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE21 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE21 LTR Lock [Disabled]
PCIE20 CLKREQ Mapping Override [Default]
PCI Express Root Port 22 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE22 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE22 LTR Lock [Disabled]
PCIE20 CLKREQ Mapping Override [Default]
PCI Express Root Port 23 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE23 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE23 LTR Lock [Disabled]
PCIE20 CLKREQ Mapping Override [Default]
PCI Express Root Port 24 [Enabled]
Topology [Unknown]
ASPM [Auto]
L1 Substates [L1.1 & L1.2]
Gen3 Eq Phase3 Method [Software Search]
UPTP [5]
DPTP [7]
ACS [Enabled]
URR [Disabled]
FER [Disabled]
NFER [Disabled]
CER [Disabled]
CTO [Disabled]
SEFE [Disabled]
SENFE [Disabled]
SECE [Disabled]
PME SCI [Enabled]
Hot Plug [Disabled]
Advanced Error Reporting [Enabled]
PCIe Speed [Auto]
Transmitter Half Swing [Disabled]
Detect Timeout [0]
Extra Bus Reserved [0]
Reserved Memory [10]
Reserved I/O [4]
PCH PCIE24 LTR [Enabled]
Snoop Latency Override [Auto]
Non Snoop Latency Override [Auto]
Force LTR Override [Disabled]
PCIE24 LTR Lock [Disabled]
PCIE20 CLKREQ Mapping Override [Default]
Audio DSP [Disabled]
HDA-Link Codec Select [Platform Onboard]
iDisplay Audio Disconnect [Disabled]
PME Enable [Disabled]
SerialIO timing parameters [Disabled]
TPM Device Selection [dTPM]
PTP aware OS [PTP Aware]
Me FW Image Re-Flash [Disabled]
Local FW Update [Enabled]
HECI Timeouts [Enabled]
Force ME DID Init Status [Disabled]
CPU Replaced Polling Disable [Disabled]
ME DID Message [Enabled]
HECI Retry Disable [Disabled]
HECI Message check Disable [Disabled]
MBP HOB Skip [Disabled]
HECI2 Interface Communication [Disabled]
KT Device [Enabled]
IDER Device [Enabled]
End Of Post Message [Send in DXE]
D0I3 Setting for HECI Disable [Disabled]
Select Camera [Ivcam]
Delay needed for Ivcam power on [0]
Delay needed for Ivcam power off [0]
Rotation [0]
DFU support [Disabled]
Wake support [Disabled]
tRd2RdSG [0]
tRd2RdDG [0]
tRd2RdDR [0]
tRd2RdDD [0]
tRd2WrSG [0]
tRd2WrDG [0]
tRd2WrDR [0]
tRd2WrDD [0]
tWr2RdSG [0]
tWr2RdDG [0]
tWr2RdDR [0]
tWr2RdDD [0]
tWr2WrSG [0]
tWr2WrDG [0]
tWr2WrDR [0]
tWr2WrDD [0]
Core PLL Voltage Offset [0]
GT PLL Voltage Offset [0]
Ring PLL Voltage Offset [0]
System Agent PLL Voltage Offset [0]
Memory Controller PLL Voltage Offset [0]
ASF support [Enabled]
USB Provisioning of AMT [Disabled]
Activate Remote Assistance Process [Disabled]
CIRA Timeout [0]
PET Progress [Enabled]
WatchDog [Disabled]
OS Timer [0]
BIOS Timer [0]
Secure Erase mode [Simulated]
Force Secure Erase [Disabled]
MEBx hotkey Pressed [Disabled]
MEBx Selection Screen [Disabled]
Hide Unconfigure ME Confirmation Prompt [Disabled]
MEBx OEM Debug Menu Enable [Disabled]
Unconfigure ME [Disabled]
Non-UI Mode Resolution [Auto]
UI Mode Resolution [Auto]
Graphics Mode Resolution [Auto]
Security Device Support [Enable]
Security Device Support [Enable]
SHA-1 PCR Bank [Enabled]
SHA256 PCR Bank [Enabled]
SHA384 PCR Bank [Disabled]
SHA512 PCR Bank [Disabled]
SM3_256 PCR Bank [Disabled]
Pending operation [None]
Platform Hierarchy [Enabled]
Storage Hierarchy [Enabled]
Endorsement Hierarchy [Enabled]
TPM2.0 UEFI Spec Version [TCG_2]
Physical Presence Spec Version [1.3]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Detect Non-Compliance Device [Disabled]
Prefetchable Memory [10]
Reserved Memory Alignment [1]
Prefetchable Memory Alignment [1]
Onboard LED [Enabled]
Q-Code LED Function [Auto]
ErP Ready [Disabled]
Restore AC Power Loss [Power Off]
Power On By PCI-E/PCI [Disabled]
Power On By RTC [Disabled]
HD Audio Controller [Enabled]
M.2_2 Configuration [PCIE mode]
Asmedia Back USB 3.1 Controller [Disabled]
When system is in working state [On]
When system is in sleep, hibernate or soft off states [Off]
5G LAN Card [Disabled]
Intel LAN Controller [Enabled]
Intel LAN PXE Option ROM [Disabled]
Detect Non-Compliance Device [Disabled]
Primary PEG [Auto]
Primary PCIE [Auto]
Network Stack [Disabled]
Legacy USB Support [Disabled]
USB Keyboard and Mouse Simulator [Disabled]
U31G1_1 [Enabled]
U31G1_2 [Enabled]
U31G1_3 [Enabled]
U31G1_4 [Enabled]
U31G1_5 [Enabled]
U31G1_6 [Enabled]
U31G1_7 [Enabled]
U31G1_8 [Enabled]
USB_9 [Enabled]
USB_10 [Enabled]
USB_11 [Enabled]
USB_12 [Enabled]
USB_13 [Enabled]
USB_14 [Enabled]
CPU Temperature [Monitor]
MotherBoard Temperature [Monitor]
VRM Temperature [Monitor]
PCH Temperature [Monitor]
T_Sensor1 Temperature [Monitor]
T_Sensor2 Temperature [Monitor]
DIMM.2 Sensor 1 [Monitor]
DIMM.2 Sensor 2 [Monitor]
Water In T Sensor [Monitor]
Water Out T Sensor [Monitor]
CPU Fan Speed [Monitor]
Chassis Fan 1 Speed [Monitor]
Chassis Fan 2 Speed [Monitor]
Chassis Fan 3 Speed [Monitor]
AIO PUMP Speed [Monitor]
CPU Optional Fan Speed [Monitor]
W_PUMP+ Speed [Monitor]
Flow Rate [Monitor]
CPU Core Voltage [Monitor]
3.3V Voltage [Monitor]
5V Voltage [Monitor]
12V Voltage [Monitor]
CPU Q-Fan Control [Disabled]
AIO_PUMP/W_PUMP+ Control [PWM Mode]
AIO_PUMP/W_PUMP+ Upper Temperature [75]
AIO_PUMP/W_PUMP+ Max. Duty Cycle (%) [100]
AIO_PUMP/W_PUMP+ Middle Temperature [60]
AIO_PUMP/W_PUMP+ Middle. Duty Cycle(%) [80]
AIO_PUMP/W_PUMP+ Lower Temperature [35]
AIO_PUMP/W_PUMP+ Min. Duty Cycle (%) [60]
Chassis Fan 1 Q-Fan Control [PWM Mode]
Chassis Fan 1 Q-Fan Source [CPU]
Chassis Fan 1 Step Up [0 sec]
Chassis Fan 1 Step Down [0 sec]
Chassis Fan 1 Speed Low Limit [Ignore]
Chassis Fan 1 Profile [Manual]
Chassis Fan 1 Upper Temperature [75]
Chassis Fan 1 Max. Duty Cycle (%) [100]
Chassis Fan 1 Middle Temperature [60]
Chassis Fan 1 Middle. Duty Cycle (%) [55]
Chassis Fan 1 Lower Temperature [30]
Chassis Fan 1 Min. Duty Cycle (%) [30]
Chassis Fan 2 Q-Fan Control [Disabled]
Chassis Fan 3 Q-Fan Control [PWM Mode]
Chassis Fan 3 Q-Fan Source [CPU]
Chassis Fan 3 Step Up [0 sec]
Chassis Fan 3 Step Down [0 sec]
Chassis Fan 3 Speed Low Limit [Ignore]
Chassis Fan 3 Profile [Manual]
Chassis Fan 3 Upper Temperature [75]
Chassis Fan 3 Max. Duty Cycle (%) [100]
Chassis Fan 3 Middle Temperature [60]
Chassis Fan 3 Middle. Duty Cycle (%) [50]
Chassis Fan 3 Lower Temperature [30]
Chassis Fan 3 Min. Duty Cycle (%) [25]
Fast Boot [Enabled]
Next Boot after AC Power Loss [Normal Boot]
Above 4G Decoding [Enabled]
Boot Logo Display [Auto]
POST Delay Time [0 sec]
Boot up NumLock State [Enabled]
Wait For 'F1' If Error [Disabled]
Option ROM Messages [Enabled]
Interrupt 19 Capture [Disabled]
Setup Mode [Advanced Mode]
Boot Sector (MBR/GPT) Recovery Policy [Local User Control]
Next Boot Recovery Action [Skip]
Launch CSM [Disabled]
OS Type [Other OS]
Setup Animator [Disabled]
Load from Profile [8]
Profile Name [Test]
Save to Profile [8]
CPU Core Voltage [Auto]
VCCSA Voltage [Auto]
BCLK Frequency [Auto]
CPU Ratio [Auto]
Cache Ratio [Auto]
Bus Interface [PCIEX16/X8_1]